PBL=1_TRANSFER
Bus Mode Register
| SWR | Software Reset. When set, the DMA Controller resets all its internal registers. SWR is read/write. It is automatically cleared after 1 clock cycle. |
| FB | Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations. FB is read/write. |
| DSL | Descriptor Skip Length. Specifies the number of HWord/Word/Dword to skip between two unchained descriptors. This is applicable only for dual buffer structure. DSL is read/write. |
| DE | SD/MMC DMA Enable. When set, the SD/MMC DMA is enabled. DE is read/write. |
| PBL | Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one SD/MMC DMA transaction. The SD/MMC DMA will always attempt to burst as specified in PBL each time it starts a Burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value to FIFOTH register. This is an encode value as follows.Transfer unit is 32 bit. PBL is a read-only value. 0 (1_TRANSFER): 1 transfer 1 (4_TRANSFERS): 4 transfers 2 (8_TRANSFERS): 8 transfers 3 (16_TRANSFERS): 16 transfers 4 (32_TRANSFERS): 32 transfers 5 (64_TRANSFERS): 64 transfers 6 (128_TRANSFERS): 128 transfers 7 (256_TRANSFERS): 256 transfers |
| RESERVED | Reserved |